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HS-65647RH
TM
Data Sheet
August 2000
File Number
2928.3
Radiation Hardened 8K x 8 SOS CMOS Static RAM
The Intersil HS-65647RH is a fully asynchronous 8K x 8 radiation hardened static RAM. This RAM is fabricated using the Intersil 1.2 micron silicon-on-sapphire CMOS technology. This technology gives exceptional hardness to all types of radiation, including neutron fluence, total ionizing dose, high intensity ionizing dose rates, and cosmic rays. Low power operation is provided by a fully static design. Low standby power can be achieved without pull-up resistors, due to the gated input buffer design. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95823. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp
Features
* Electrically Screened to SMD # 5962-95823 * QML Qualified per MIL-PRF-38535 Requirements * 1.2 Micron Radiation Hardened SOS CMOS - Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . >1 x 1011 rad(Si)/s - Single Event Upset . . . . . . . . < 1 x 10-12 Errors/Bit-Day * Latch-up Free * LET Threshold . . . . . . . . . . . . . . . . . . >250 MEV/mg/cm2 * Low Standby Supply Current . . . . . . . . . . . . . 10mA (Max) * Low Operating Supply Current . . . . . . . . . .100mA (2MHz) * Fast Access Time . . . . . . . . . . . . . 50ns (Max), 35ns (Typ) * High Output Drive Capability * Gated Input Buffers (Gated by E2) * Six Transistor Memory Cell * Fully Static Design
Ordering Information
ORDERING NUMBER 5962F9582301QXC 5962F9582301QYC 5962F9582301VXC 5962F9582301VYC INTERNAL MKT. NUMBER HS1-65647RH-8 HS-965647RH-8 HS1-65647RH-Q HS9-65647RH-Q TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
* Asynchronous Operation * CMOS Inputs * 5V Single Power Supply * Military Temperature Range . . . . . . . . . . . -55oC to 125oC * Industry Standard JEDEC Pinout
Functional Diagram
AI ROW ROW DECODER 128 X 512 MEMORY ARRAY
HS1-65647RH/PROTO HS1-65647RH/PROTO HS9-65647RH/PROTO HS9-65647RH/PROTO
TRUTH TABLE E1 X 1 0 0 0 E2 0 1 1 1 1 G X X 1 0 X W X X 1 1 0 MODE Low Power Standby Disabled Enabled Read Write
E1 G W CONTROL CIRCUIT E2 I/O7 AI COL I/O0 INPUT DATA CIRCUIT COLUMN I/O COLUMN DECODER
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HS-65647RH Pinout
HS1-65647RH 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T28 TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 28 VDD 27 W 26 E2 25 A8 24 A9 23 A11 22 G 21 A10 20 E1 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 2 3 4 5 6 7 8 9 10 11 12 13 14 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3
HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F28 TOP VIEW
A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14
HS9A-65647RH 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K36.A TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ0 DQ1 DQ2 GND 2 3 4 5 6 7 8 9
1
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ0 DQ1 DQ2 GND
10 11 12 13 14 15 16 17 18
2
HS-65647RH Timing Waveforms
TAVAX A ADDRESS 1 ADDRESS 2
TAVQV Q DATA 1
TAXQX DATA 2
FIGURE 1. READ CYCLE I: W, E2 HIGH; G, E1 LOW
TAVAX A TAVQV E1 TE1LQV TE1LQX E2 TE2HQV TE2HQX G TGLQV TGLQX Q TGHQZ TE2LQZ TE1HQZ
FIGURE 2. READ CYCLE II: W HIGH
TAVAX A TAVWL W TWLWH TWHAX
E1
E2 TWHQX TDVWH D TWLQZ Q TWHDX
FIGURE 3. WRITE CYCLE I: LATE WRITE
3
HS-65647RH Timing Waveforms
(Continued)
TAVAX A TAVE1L TAVE2H W TE1LE1H TE1HAX
E1
E2 TDVE1H TE1HDX D
FIGURE 4. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1
TAVAX A TAVE2H W TAVE2L TE2HE2L TE2LAX
E1
E2 TDVE2L D TE2LDX
FIGURE 5. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2
4
HS-65647RH Typical Performance Curves
13 12 11 10 9 IDDSB (mA) 8 7 6 5 4 3 2 1 0 0 200 400 600 800 1000 1200 1400 TOTAL DOSE (KRAD) 0 0.1 0.1 10 100 1 IDDSB (mA) 5 4 3 2 6
TA = 25oC, Unless Otherwise Specified
7
ANNEAL TIME (HOURS)
FIGURE 6.
100 90 80 70 IDDEN (mA) 60 50 40 30 20 10 -60 -40 -20 0 20 40 60 80 100 120 0 -60 -40 -20
FIGURE 7.
10 9 8 7 IDDSB (mA) 6 5 4 3 2 1 0
0
20
40
60
80
100
120
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE 8.
FIGURE 9.
120 110 100 90 IDDOP (mA) 80 70 60 50 40 30 20 -60 -40 -20 0 20 40 60 80 100 120 IDDOP (mA)
106 102 98 94 90 86 82 78 74 70 66 62 58 0 1 2 3 4 5 6 7 8 9 10
TEMPERATURE (oC)
FREQUENCY (MHz)
FIGURE 10.
FIGURE 11.
5
HS-65647RH Burn-In Circuits
HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP
1 NC F13 F8 F7 F6 F5 F4 F3 F2 F1 F14 F14 F14 R2 R2 R2 2 3 4 5 6 7 8 9 10 11 12 13 14 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R2 R2 R2 R2 R2 F0 F11 F14 F14 F14 F14 F14 NC NC NC F9 F10 F12 VDD NC F0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD W E2 A8 A9 A11 28 27 26 25 24 23
HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP
VDD
G 22 A10 21 E1 20 DQ7 DQ6 DQ5 DQ4 DQ3 19 18 17 16 15 NC NC NC NC NC
DYNAMIC CONFIGURATION NOTES: 1. 2. 3. 4. 5. 6. VDD = 5.5V Min. R = 10k 10%, except R2 = 47k 10%. VIH: VDD 0.5V, VIL: 0.4V 0.4V. F0 = 100kHz 10%, 50% Duty Cycle. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2. F0 = inverted F0. HS-65647RH 36 LEAD FLATPACK
VDD 1 2 NC F13 F8 F7 F6 F5 F4 F3 F2 F1 F14 R2 F14 R2 F14 R2 NC 3 4 5 6 7 8 9 10 11 12 13 VSS VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 VSS 36 VDD 35 NC 34 W 33 E2 32 A8 31 A9 30 A11 29 G 28 A10 27 E1 26 DQ7 25 DQ6 24 DQ5 23 DQ4 22 DQ3 21 VDD 20 VSS 19 R2 R2 NC F0 F9 F10 F12 F0 F11 F14 F14 NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13
STATIC CONFIGURATION NOTES: 7. VDD = 5.5V Min. 8. R = 10k 10%.
HS-65647RH 36 LEAD FLATPACK
VDD VSS VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 VSS 36 VDD 35 NC 34 W 33 E2 32 A8 31 A9 30 A11 29 G 28 A10 27 E1 26 DQ7 25 DQ6 24 DQ5 23 DQ4 22 DQ3 21 VDD 20 VSS 19 NC NC NC NC NC NC
14 DQ1 15 DQ2 16 NC 17 VDD 18 VSS
R2 F14 R2 F14 R2 F14
14 DQ1 15 DQ2 16 NC 17 VDD 18 VSS
DYNAMIC CONFIGURATION NOTES: 9. 10. 11. 12. 13. 14. VDD = 5.5V Min. R = 10k 10%, except R2 = 4.7k 10%. VIH: VDD 0.5V, VIL: 0.4V 0.4V. F0 = 100kHz 10%, 50% Duty Cycle. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2. F0 = Inverted F0. NOTES:
STATIC CONFIGURATION 15. VDD = 5.5V Min. 16. R = 10k 10%.
6
HS-65647RH Irradiation Circuit
HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP
VDD
NC
1 NC 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 DQ0 12 DQ1 13 DQ2 14 VSS
VDD 28 W 27 E2 26 A8 25 A9 24 A11 23 G 22 A10 21 E1 20 DQ7 19 DQ6 18 DQ5 17 DQ4 16 DQ3 15
NOTES: 17. VDD = 5.5V 0.5V R = 10k 10%. 18. Group E sample size is two die/wafer.
Test Patterns
MARCH (II) PATTERN
After a background of zeros is written, each cell (from beginning to end in sequence) is read, written to a one and reread. When the array is full of ones each cell (from the end to the beginning) is read, restored to a zero and reread. After this the pattern is repeated but with complemented data. This is pattern then repeated but using complemented data.
GALCOL PATTERN (Column Galloping Pattern)
After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the column. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data.
MASEST PATTERN (Multiple Address Select Pattern)
A checkerboard pattern is written into the memory. Then the first cell is read, then its binary address complement is read. The second cell is read and then its binary address complement is read. This pattern of incrementing the address and then reading its binary address complement is repeated until the entire memory is read. This is then repeated but using a checkerboard bar pattern.
CHECKERBOARD PATTERN and CHECKERBOARD BAR
A checkerboard is written (101010) into the memory and then the pattern is read back. This is then repeated but using complemented data.
GALROW PATTERN (Row Galloping Pattern)
After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the row. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. 7
HS-65647RH Metallization Topology
DIE DIMENSIONS: 313 mils x 291 mils x 21 mils 1mil METALLIZATION: Type: Al/Si/Cu Metal 1 Thickness: 7500A 2kA Metal 2 Thickness: 10kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.5 x 105 A/cm2
Metallization Mask Layout
HS-65647RH
(28) VDD (23) A11 (2) A12 (25) A8 (24) A9 (26) E2 (27) W (22) G (7) A3 (6) A4 (5) A5 (4) A6 (3) A7
NC
NC VSS VDD NC
VSS
VDD
DQ0 (11)
DQ1 (12)
DQ2 (13)
DQ3 (15)
DQ4 (16)
DQ6 (18)
DQ7 (19)
VSS (14)
D15 (17)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 8
A10 (21)
A0 (10)
A2 (8)
A1 (9)
E (20)
VDD
NC

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